1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, P channel high voltage transistors with improved breakdown voltages. The present invention further relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 4 is a sectional view showing a conventional semiconductor device including a P channel high voltage transistor, and a pulldown resistor provided between the P channel high voltage transistor and a V.sub.EE terminal. Such a P channel high voltage transistor is used, for example, in a switch of a fluorescent character display tube.
A first N type well region 2 and a second N type well region 21 are provided on the main surface of a P type semiconductor substrate 1. Field oxide films 3A, 3B and 3C are provided on the main surface of first N type well region 2. A P type source region 5 and a P type drain region 6 are formed spaced apart from each other on the opposite sides of field oxide film 3B on the main surface of first N type well region 2. A P type impurity injection region 7b having an impurity concentration lower than that of P type drain region 6 is provided immediately under field oxide film 3B so as to be connected P type drain region 6. P type source region 5 and P type impurity injection region 7b are formed to be spaced apart from each other so as to form a channel region. Also provided immediately under field oxide film 3A is a P type impurity injection region 7a having an impurity concentration lower than that of P type source region 5 so as to be connected to P type source region 5. Also provided immediately under field oxide film 3C is a P type impurity injection region 7c having an impurity concentration lower than that of the P type drain region so as to be connected to P type drain region 6.
A gate electrode 8 is provided between P type source region 5 and P type drain region 6 on first N type well region 2, with a thin oxide film provided therebetween. Gate electrode 8 is provided such that a part of the electrode overlaps field oxide film 3B.
An N.sup.+ ion injection region 4a having a concentration higher than an N type impurity concentration of N type well region 2 is provided under P type source region 5 and the channel in N type well region 2. An N.sup.+ ion injection region 4b having a concentration higher than the N type impurity concentration of the N type well is provided under P type drain region 6 in N type well region 2.
Field oxide films 3D, 3E and 3F are provided in the main surface of second N type well region 21. An output side P.sup.+ region 9 and a V.sub.EE power source side P.sup.+ region 10 are provided at the opposite sides of field oxide film 3E in the main surface of second N type well region 21. A P type impurity resistive layer 7e having a concentration lower than the P type impurity concentration of P.sup.+ regions 9 and 10 is provided immediately under field oxide film 3E in order to connect output side P.sup.+ region 9 and V.sub.EE power source side P.sup.+ region 10. Also provided immediately under field oxide film 3D is a P type impurity injection region 7d connected to output side P.sup.+ region 9. Provided also under field oxide film 3F is a P type impurity injection region 7f connected to V.sub.EE power source side P.sup.+ region 10 and having a concentration lower than the P type impurity concentration of V.sub.EE power source side P.sup.+ region 10. Provided on field oxide film 3E is an electrode 11 formed of polysilicon. A voltage of the same volume as that to be applied to P type impurity resistive layer 7e is applied to electrode 11, thereby preventing damage of P type impurity resistive layer 7e. Electrode 11 is provided for serving such a function. N.sup.+ ion injection regions 4c and 4d having a concentration higher than the N type impurity concentration of second N type well 21 are provided under output side P.sup.+ region 9 and V.sub.EE power source side P.sup.+ region 10 in second N type well region 21.
FIG. 5 is a circuit diagram showing the above-described P channel high voltage transistor, and a pulldown resistor between the P channel high voltage transistor and the V.sub.EE terminal. In the figure, reference numeral 12 denotes the P channel high voltage transistor, reference numeral 13 denotes the pulldown resistor, 14 denotes an output terminal, 15 denotes a V.sub.EE power source terminal and 16 denotes a power source terminal. Power source terminal 16 is supplied with a power source voltage vcc. Such a switch is used as a switch for a fluorescent character display tube as described above. An application of the power source voltage Vcc of 5 V and an appropriate voltage to gate electrode 8 turns on P channel high voltage transistor 12, thereby turning on the fluorescent character display tube. Then, upon application of a high voltage (-35 V) to output terminal 14 and V.sub.EE power source terminal 15, the voltage on output terminal 14 is drawn by pulldown resistor 13 to turn off the fluorescent character display tube.
In thus structured semiconductor memory device, a high voltage applied to a part between output terminal 14 and V.sub.EE power source terminal 15 results in an application of a high voltage to P.sup.+ drain region 6 of P channel high voltage transistor 12, output side P.sup.+ region 9 and V .sub.EE power source side P.sup.+ region 10 of pulldown resistor 13. However, because of N.sup.+ ion injection region 4a and P type impurity injection region 7b, breakdown hardly occurs between a portion deep in the channel and a channel N edge on the side of P.sup.+ drain region 6.
A conventional method of forming N.sup.+ ion injection region 4a of the P region high voltage transistor shown in FIG. 4 will be described in the following.
With reference to FIGS. 6A and 6B, N.sup.+ ion injection region 4a is conventionally formed by injecting N type impurities in the main surface of P type semiconductor substrate 1. No N.sup.+ ion injection region is formed under field oxide films 3A, 3B, 3C, 3D, 3E and 3F because a thickness of these films is too large to pass N type impurities. N.sup.+ ion injection regions 4a, 4b, 4c and 4d are formed under an oxide film of a small thickness.
The conventional method of forming an N.sup.+ ion injection region is conducted in a manner as described above and has the following problems.
With reference to FIG. 6B, N.sup.+ ion injection regions 4b, 4c and 4d are formed at undesired parts simultaneously with a formation of N.sup.+ ion injection region 4a.
In addition, a bird's beak 30 of field oxide film 3B is so small in thickness that N type impurities 17 pass therethrough to be injected in an edge portion 31 of P type impurity injection region 7b. As a result, the P type impurities and the N type impurities cancel with each other to result in elimination of P type impurity injection region 7b at a portion 32 under bird's beak 30 as shown in FIG. 6B.
The foregoing problems have such adverse effects on an obtained semiconductor device.
With reference to FIG. 4, since N.sup.+ ion injection region 4b is provided deep in second N type well region 21 under P.sup.+ drain region 6, a breakdown voltage between P.sup.+ drain region 6 and semiconductor substrate 1 is reduced for a reason unknown.
In addition, also on the side of the pulldown resistor 13, since N.sup.+ ion injection region 4c is provided under output side P.sup.+ region 9, a breakdown voltage between output side P.sup.+ region 9 and substrate 1 is reduced for a reason unknown. Similarly, with N.sup.+ ion injection region 4d under V.sub.EE power source side P.sup.+ region 10, a breakdown voltage between V.sub.EE power source side P.sup.+ region 10 and substrate 1 is reduced for a reason unknown.
Furthermore, with reference to FIG. 6B, the portion 32 from which the edge portion of P type impurity injection region 7b is eliminated, an electric field is intensified to cause breakdown to prevent the breakdown voltage from being maintained.